1. Field of the Invention
The present invention relates to an image coding device for coding binary image data by arithmetic coding.
2. Description of the Related Art
A conventional image coding device by arithmetic coding is explained by referring to FIG. 3 to FIG. 7, and FIG. 13 to FIG. 15. FIG. 3 is a flowchart showing first coding process, FIG. 4 is a diagram showing reference pixel and coding pixel, FIG. 5 is a data diagram showing data of prediction table, FIG. 6 is a flowchart showing first normalizing process, FIG. 7 is a flowchart showing first code output process, FIG. 13 is a block diagram of a conventional image coding device, FIG. 14 is a flowchart showing operation of conventional arithmetic coding unit, and FIG. 15 is a flowchart showing remaining code output process.
A conventional image coding device 7 comprises a conventional arithmetic coding unit 8, and a prediction table 8a. Image data is stored in an image memory 7a. 
The operation of the image coding device 7 is explained by referring to FIG. 14.
First, contents of registers in the image coding device are initialized as shown in formula 1 to formula 9. (S101)NUM=0  (1)A=0x100  (2)CT=8  (3)CS=0  (4)C=0  (5)BUFFER=0x00  (6)TEMP=0  (7)Amps=0  (8)Alps=0  (9)
Herein, “NUM” is a register for counting the number of input pixels, and “A” is the content of a register showing the effective region width. The initial value of “A” is “0x100” expressing the width of number line from 0 to 1, and the decimal part of the number line has a resolution of 8 bits. The numerical value following “0x” is in hexadecimal notation. “CT” is the content of a counter for code output processing, “CS” is the content of a hold counter for carry propagation, “C” is the content of a 17-bit code register, “BUFFER” is the content of a buffer for 8-bit code output, and “TEMP” is the content of a 9-bit temporary register. “Amps” denotes the number line width of superiority symbol (MPS), and “Alps” represents the number line width of inferiority symbol (LPS).
After initialization at step S101, first coding process is executed (S102).
Referring to FIG. 3, first coding process at step S102 is explained.
First, a reference pixel and an input pixel to the coding device are acquired, and pixel value “PIX” is obtained (S11). The value of the reference pixel is given as the address, and from the prediction table 8a, the value of “MPS” and the value of “SRL” (shift right logical) are acquired. The reference pixel consists of three pixels at every 8 pixels from the coding pixel as shown in FIG. 4. These pixel values are supposed to be addresses A2, A1, A0 of the prediction table 8a. FIG. 5 shows the composition of the prediction table 8a. The addresses of the prediction table 8a are 0x0 to 0x7, and the data width is 4 bits. Three out of these four bits are the value of “SRL”, and one bit is the value of “MPS”.
Consequently, from the obtained value of “SRL”, the values of “Alps” and “Amps” are calculated (S12). Next, the value of “MPS” and the value of “PIX” are compared (S13), and when matched, the effective region width “A” is updated to the superiority symbol width “Amps” (S14). And if not matched, the effective region width “A” is updated to the inferiority symbol width “Alps”, and the value of C-register is updated to C=C+Amps (S16). Then, to see if “A” is less than ½ or not, A<0x80 is judged to be true or false (S15). When the result of judgement is true, normalizing by first normalization (S17), “A” is put back to ½ or more. Otherwise, the first coding process is terminated.
FIG. 6 is a flowchart showing the operation of first normalization process S17.
First, shifting “A” and “C” by one bit to left, the value of “CT” is subtracted by one (S21). Next, by first code output process (S22), the process at step S21 and step S22 is repeated until the value of “A” becomes 0x80 or more at step S23.
Referring now to FIG. 7, the operation of first code output process at step S22 is explained.
First evaluating whether the value of “CT” is 0 or not (S31), if not 0, code output is not processed, and the code output process is terminated. When the value of “CT” is 0, “C” is shifted to right by 19 bits, and stored in a TEMP register (S32). The value of “TEMP” is evaluated to be greater than 0x FF or not (S33). When the value of “TEMP” is greater than 0x FF, the value of (BUFFER+1) is issued by one byte, and since the value of TEMP is more than 0x FF, a carry occurs, and 0x00 is issued for the number of times of hold (CS times), and the value of “BUFFER” is updated to the value of the lower 8 bits of “TEMP” (S34). When the value of “TEMP” is smaller than 0x FF, it is judged if the value of TEMP is equal to 0x FF or not (S36). When the value of “TEMP” is equal to 0x FF, considering a carry, the value of the number of times of hold “CS” is incremented by one, and the code output remains to be held (S37). In the evaluation at step S36, if the value of “TEMP” is smaller than 0x FF, the value of “BUFFER” is issued by one byte, and since “TEMP” is 0x FF and carry does not occur, and 0x FF is issued for the number of times of hold (CS times), and the value of “BUFFER” is updated to the value of “TEMP” (S38). After each code output by the value of “TEMP”, the value of “C” is updated to C&0x FF, and the value of “CT” is updated to 8, so that the first code output process (S22) is terminated (S35). Herein, “&” is an operator indicating the logical product AND.
After the first coding process in this manner, the value of “NUM” is incremented by one (S103 in FIG. 14). The value of “NUM” is evaluated to be equal to the number of pixels of the setting process (S104), and if not equal, steps S102 and S103 are repeated. If equal, the remaining code output is processed (S105).
Referring to FIG. 15, the remaining code output process (S105) is explained.
In the remaining code output process, output of the code is made from the information in A-register and the coded data remaining in the C-register. In TEMP register, in the first place, (A−1+C)&0x1FF00 is stored (S201), and the value of “TEMP” is judged to be smaller than the value of “C” or not (S202). When the value of “TEMP” is smaller than the value of “C”, the value of “C” is updated to TEMP+0x80 (S203). When the value of “TEMP” is not smaller than the value of “C”, the value of “C” is updated to “TEMP” (S208). “C” is shifted to left by CT bits and “C” is shifted to right by 8 bits and stored in TEMP register (S204). Then, “TEMP” is judged to be larger than 0x FF or not (S205). When “TEMP” is larger than 0x FF, a carry occurs, and first (BUFFER+1) is issued by one byte code, and 0x00 is issued for the number of times of hold (CS times) (S206). When “TEMP” is smaller than 0x FF, carry does not occur, and first “BUFFER” is issued by one byte code, and 0x FF is issued for the number of times of hold (CS times) (S209). Finally, after shifting “C” to right by 8 bits, lower 8 bits of “C” are issued (S207), and the remaining code output process (S105) is terminated. That is, the process by the conventional arithmetic coding unit 8 is terminated.
In this conventional image coding device 7, however, after input of image data, the remaining code output process (S105 in FIG. 14) is required for code output from the A-register information and the remaining code data stored in the C-register. As a result, for hardware configuration, it leads to increase in the circuit scale and decline of operation clock. To solve such problems, the image coding device not requiring remaining code process has been demanded.